Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP

<div>Comparison of the CGP circuits of Config2 8-bit activation functions with conventional implementations for the same data format in (a) FPGA flow and (b) ASIC flow. Please note that hls4ml utilizes an additional 16 BRAMs that are not captured here.</div>

IET Computers & Digital Techniques

fig17

Figure 17

Figure 17: Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP 