Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP

Table 5

Average number of nodes for CGP synthesized circuits under Config2 format, which is required to achieve full fitness.

Function	CGP nodes	4 bit	5 bit	6 bit	7 bit	8 bit
Gaussian	Basic gates	10	20	39	80	144
	Std cells	7	14	28	56	105
GeLU	Basic gates	10	14	18	31	54
	Std cells	7	8	12	22	36
Sigmoid	Basic gates	7	14	27	47	98
	Std cells	4	8	15	28	61
Softplus	Basic gates	5	8	23	47	90
	Std cells	4	6	14	28	49
tanh	Basic gates	6	15	35	64	131
	Std cells	4	10	20	42	82