Research Article
Dimension Reduction Using Quantum Wavelet Transform on a High-Performance Reconfigurable Computer
Table 3
Comparison of the proposed work against previous works of FPGA emulation.
| Reported work | Algorithm | Number of qubits | Precision | Frequency (MHz) | Emulation time (sec) |
| Fujishima [48] | Shor’s factoring | — | — | 80 | 10 |
| Khalid et al. [49] | QFT | 3 | 16 bit fixed pt. | 82.1 | 61E − 9 | Grover’s search | 3 | 16 bit fixed pt. | 82.1 | 84E − 9 |
| Aminian et al. [50] | QFT | 3 | 16 bit fixed pt | 131.3 | 46E − 9 |
| Lee et al. [51] | QFT | 5 | 24 bit fixed pt. | 90 | 219E − 9 | Grover’s search | 7 | 24 bit fixed pt. | 85 | 96.8E − 9 |
| Silva et al. [52] | QFT | 4 | 32 bit floating pt. | — | 4E − 6 |
| Pilch et al. [53] | Deutsch | 2 | — | — | — |
| Mahmud et al. [22] | QFT | 5 | 32 bit floating pt. | 233 | 4.63E − 4 | Grover’s search | 5 | 32 bit floating pt. | 233 | 4.38E − 7 |
| Proposed work | QFT | 20 | 32 bit floating pt. | 233 | 18.4 | QHT | 20 | 32 bit floating pt. | 233 | 0.477 | Grover’s search | 22 | 32 bit floating pt. | 233 | 7.5E04 |
|
|
Results obtained at a later time to publication. |