Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

Table 2

Interesting features of simulators for high-performance computing architectures. For the nonobvious columns, Parallel/Sequential means the simulator core can be executed either in parallel or sequential by the host processor. Full System means taking into account all events, including the OS.

Simulator	Parallel/sequential	Single-core/multicore	Full system	Simulation methodology
COTSon [16]	Parallel	Multicore	Yes	Decoupled-functional first
GEMS [25]	Sequential	Multicore	Yes	Decoupled- timing first
Graphite [41]	Parallel	Multicore	No	Not decoupled- trace-driven
SimpleScalar [24]	Sequential	Single-core	No	Not decoupled- execution driven
MPTLsim [26]	Sequential	Multicore	No	Not decoupled- timing first
SlackSim [23]	Parallel	Single-core	No	Not decoupled- timing first