Research Article

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise—Designing a Computer Architecture via HLS)

Table 4

COTSon architectural parameter.

ParameterDescription

SoC1 core connected by shared-bus, IO-bus, MC, high-speed transceivers
Core3 GHz, in-order super-scalar
Branch predictorTwo levels (history length = 14 bits, pattern history
Table = 16 KiB, 8-cycle miss-prediction penalty)
L1 cachePrivate I-cache 32 KiB, private D-cache 32 KiB, 2 ways, 3-cycle latency
L2 cachePrivate 2, 8, 32, 64, 256, 1024 KiB, 4 ways, 5-cycle latency
L3 cacheShared 4 MiB, 4 ways, 20-cycle latency
Coherence protocolMOESI
Main memory1 GiB, 100-cycle latency
I-L1-TLB, d-L1-TLB64 entries, direct access, 1-cycle latency
L2-TLB512 entries, direct access, 1-cycle latency
Write/read queues200 Bytes each, 1-cycle latency