Automatic Pipelining and Vectorization of Scientific Code for FPGAs

Figure 6

TIR code and DFG of the synthetic example. The TIR shows 4 kernels connected in a coarse-grained pipeline in a top kernel, which is connected to global memory streams in the main function. The DFG is generated by the backend from the TIR, and only the top-level kernel is shown here. The tuple of three integers with each node is the scheduling parameters (latency, firing-interval, and start-delay) inferred from the code and used by the backend for scheduling and RTL code generation.