Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications

Algorithm 1

Horizontal shuffle NMSA.

(1)	Initialize all , and Itermax
(2)	for i = 1 to Itermax do
	Horizontal processing (C2V computation):
(3)	for each check node
(4)	for each variable node j connected to ci
(5)	Calculate &
(6)	end for line 4
(7)	for each variable node j connected to
(8)
(9)	end for line 7
	Vertical processing (V2C computation) and LLR update:
(11)	for each variable node j connected to ci
(12)	for every check node ca connected to j
(13)
(14)	end for line 12
(15)
(16)	for every check node ca connected to j
(17)
(18)	end for line 16
(19)	end for line 11
(20)	end for line 3
	Hard decision:
(21)	for each variable node
(22)	Make hard decision if sign() > 0 then j = 1; else j = 0
(23)	end for line 19
	Parity check equations (Syndrome) and stopping criteria:
(24)	if H·v^T = 0 then break else i = i + 1
(25)	end for line 2