Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications

Table 2

CPU run-time in cycles spent by instruction and memory accesses.

Code sizes	Total cycles	Instruction cycles	Data read memory accesses	Data write memory accesses	L1 memory cache miss	Last level memory cache miss
(9216, 4608)	105 128 98	3 727 900	5 137 660	1 394 103	24 275	105
(4608, 2304)	5 252 338	1 866 554	2 563 633	695 571	12 136	52
(2304, 1152)	2 614 171	928 109	1 276 110	346 712	6 064	26
(1152, 576)	1 306 863	465 771	635 694	173 865	3 023	13
(576, 288)	650 901	231 316	317 418	86 468	1 505	6