Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications

Table 4

CPU run-time reduction compared to previous works.

Code size	CPU cycles previous work	CPU cycles proposed work	Reduction ratio
(9216, 4608)	1.05 × 10^7	3.45 × 10^6	66.67%
(2304, 1152)	2.6 × 10^6	8.5 × 10^5	66.00%
(576, 288)	6.5 × 10^5	2.1 × 10^5	67.7%