A Substrate-and-Gate Triggering NMOS Device for High ESD Reliability in Deep Submicrometer Technology

Table 1

(a) Resistance SGTNMOS 𝐼_𝑡2 with different pickup styles. (b) RC SGTNMOS 𝐼_𝑡2 with different pickup styles. (c) GGNMOS 𝐼_𝑡2 with different pickup styles.

(a)

Normal pickup Resistance 𝑅𝑔 (Ω)	500	2 k	5 k	10 k	40 k	100 k
R-SGT 𝐼𝑡2 (A)	3.8	3.8	3.59	3.93	3.85	3.79
Pickup style 𝑅𝑔 (Ω)	Butting 1 k	Butting 10 k	Inserted 1 k	Inserted 10 k
R-SGT 𝐼𝑡2 (A)	3.78	3.79	3.92	3.91

(b)

𝑅𝑔/𝐶𝑔 (Ω/F)	10 k/20 p	20 k/10 p	40 k/5 p	95 k/1.2 p
Normal RC-SGT 𝐼𝑡2 (A)	3.75	3.74	3.79	3.77
Pickup style	Butting	Inserted
RC-SGT 𝐼𝑡2 (A)	3.75	3.75

(c)

𝐼𝑡2 (A)	Normal	Butting	Inserted
GGNMOS	3.04	2.92	1.09