Optimization of CNFET Parameters for High Performance Digital Circuits

Table 4

The propagation delay of inverter, 2-input NAND, 2-input NOR gate for Si-MOS, pure-CNFET, and hybrid configuration.

	Delay (xE-11S)
	Si-MOSFET	Pure-CNFET		Hybrid; NMOS-PCNFET
	32 nm CMOS	Nonoptimized	Optimized
Inverter	14.6	3.80	9.51	5.94
2-input NAND	19.95	11.94	16.09	9.91
2-input NOR	20.50	7.54	9.95	10.17