Optimization of CNFET Parameters for High Performance Digital Circuits

Table 5

The power dissipation of inverter, 2-input NAND, and 2-input NOR gates for Si-MOS, pure-CNFET, and hybrid configuration.

	Power (xE-07W)
	Si-MOSFET	Pure-CNFET		Hybrid; NMOS-PCNFET
	32 nm CMOS	Nonoptimized	Optimized
Inverter	5.83	13.19	2.61	9.76
2-input NAND	13.98	17.26	3.53	12.35
2-input NOR	10.05	16.14	3.88	14.23