Optimization of CNFET Parameters for High Performance Digital Circuits

Table 6

The power delay product of inverter, 2-input NAND, and 2-input NOR gate for Si-MOS, pure-CNFET, and hybrid configuration.

	PDP (xE-17J)
	Si-MOSFET	Pure-CNFET		Hybrid; NMOS-PCNFET
	32 nm CMOS	Nonoptimized	Optimized
Inverter	8.51	5.01	2.48	5.79
2-input NAND	27.80	20.61	5.68	12.23
2-input NOR	20.60	12.16	3.86	14.47