Modeling and Performance Analysis of a Fault-Tolerant 3D Photonic Network-on-Chip Based on Hybrid Photonics–Plasmonics

Table 1

Electrical layer simulation parameter setting.

Electronic control layer
Clock frequency	1 GHz
Packet size	32\64\128\256\512 bit
Energy consumed	Dynamic_Electri_consumption_send	100 fJ/bit
	Dynamic_Electri_consumption_receive	100 fJ/bit
	Static_Electri_consumption_storage	2 fJ/bit
	Static_Electri_consumption_ctro	5 fJ/bit
	Dynamic_SPP_switch_consumption	13.1 fJ/bit
	Static_SPP_switch_consumption	3 fJ/bit