| | Step 1: The no of input bits is verified. |
| | Step 2: A process of adding additional bits to the messaging input (MI) such that the total data length is equivalent to 512 multiples |
| | Step 3: m is the result of adding 64 bit MI to the output of step 2. |
| | Step 4: The blocks from m to b are separated (512 bits each). |
| | Step 5: This is a list of blocks, each with 32 bits, from b to x (16). |
| | Step 6: The algorithm has four rounds, each with 16 steps (64 steps in total). |
| | Step 7: There are four hex-encoded shift registers, each with a capacity of 32 bits. |
| | reg a = [7 6 5 4 3 2 1 0] 32- bits [a] = |
| | reg b = [f e d c 8 a 9 7] 32- bits [b] = |
| | reg c = [8 9 a b c d e f] 32- bits [c] = |
| | reg d = [0 1 2 3 4 5 6 7] 32‐ bits [d] = |
| | Step 8: aa, bb, cc, & dd are used to temporarily store the a, b, and c values. |
| | Step 9: Several variables f, , h, and I are involved in the algorithm processing. Shown below is a one-step operation: |
| | a = b + (a + f(b, c, d)) + [k] + t[i] <<< S |
| | where. |
| | [k] is the 32 bit word of |
| | <<<S ← left circular shift of S bits. |
| | After each round’s final output is added, the first round’s input is used as the output. |
| | Step 10: The output bit depth is increased to 128 bits |
