Hybrid Network-on-Chip: An Application-Aware Framework for Big Data

Table 2

System parameters.

	Buffered NoC/bufferless NoC
Topology	2D mesh, 8 × 8 size
Routing algorithm	X-Y routing, flit-by-flit
Routing latency	2 cycles
Core	Out-of-order, 16 MSHR, 128 instruction windows size
	L1 I-cache and D-cache: 32 KB, 64 B line-size, 2-way, LRU, 2-cycle latency
L1 cache	Private
L2 cache	Per-block interleaving shared, distributed, 64 B line-size, perfect