Analysis of the Time Series Generated by a New High-Dimensional Discrete Chaotic System

Wang, Chuanfu; Fan, Chunlei; Feng, Kai; Huang, Xin; Ding, Qun

doi:https://doi.org/10.1155/2018/9818520

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Research Article | Open Access

Volume 2018 | Article ID 9818520 | https://doi.org/10.1155/2018/9818520

Analysis of the Time Series Generated by a New High-Dimensional Discrete Chaotic System

Chuanfu Wang,¹Chunlei Fan,¹Kai Feng,¹Xin Huang,¹and Qun Ding¹

Academic Editor: Christos Volos

Received19 Dec 2017

Revised14 Jun 2018

Accepted04 Jul 2018

Published27 Aug 2018

Abstract

The chaotic behavior of low-dimensional digital chaotic systems is seriously degraded, and the output sequence has a short period. In this study, a digital sequence generator based on a high-dimensional chaotic system is proposed to ensure performance and security. The proposed generator has low resource consumption, and the digital pseudo-random output sequence has a large period. To avoid the nonchaotic state, the multistability in the high-dimensional discrete chaotic system is analyzed. The statistical performance of the output sequence of the proposed digital high-dimensional chaotic system is evaluated, and the results demonstrate that it is a suitable candidate for a long-period pseudo-random sequence generator.

1. Introduction

Random sequence generators are used in several engineering applications including compressed sensing, image encryption, secure communication, spread-spectrum communication, and distance measurement [1–7]. They can be classified into true random sequence generators and pseudo-random sequence generators. True random sequence generators are based on physical sources, such as resistor thermal noise, atmospheric noise, and race hazard circuits. Although true random sequence generators are highly secure, their implementation is overly complex. Moreover, they are difficult to control. By contrast, pseudo-random sequence generators are based on seeds (initial values). A given seed completely determines the behavior of the pseudo-random sequence generator. Pseudo-random sequence generators are designed by using certain mathematical algorithms, such as linear feedback shift register (LFSR), nonlinear feedback shift register (NLFSR), linear congruence, nonlinear congruence, and BBS (Blum Blum Shub). These design methods are quite limited because they depend on the corresponding algorithm. LFSR is a linear function. It can be quickly reconstructed by the Berlekamp–Massey algorithm without prior knowledge of the seed. NLFSR, linear congruence, nonlinear congruence, and BBS are one-dimensional discrete maps. They generate a large-period pseudo-random sequence at high computational cost. With the rapid development of networks, the speed and period of pseudo-random sequence generators have attracted increasing attention. Therefore, the design method of pseudo-random sequence generators should be improved to meet the requirements of fast big data processing.

Chaos is a universal phenomenon in nonlinear systems. Chaotic systems exhibit a large number of special behaviors, such as initial value sensitivity, orbital ergodicity, and aperiodicity [8]. These behaviors are in accordance with the confusion and diffusion proposed by Shannon [9]. Therefore, chaotic systems are considered a new method for constructing pseudo-random sequence generators. A large number of chaotic systems have been discovered, and several chaos control methods have been proposed. Compared with other pseudo-random sequence generators, chaotic pseudo-random sequence generators allow a large variety of design choices. Therefore, the standards can be focused not only on the randomness of the output sequence but also on speed, period, and resource consumption. A chaotic pseudo-random sequence generator should be appropriately optimized to meet the requirements of different engineering applications, particularly big data processing.

Chaotic systems can be classified into continuous and discrete systems. For digital applications, continuous chaotic systems should first be discretized and then digitized. Discretization methods include the Euler method [10] and the Runge–Kutta method [11]. By contrast, discrete chaotic systems require digitizing only and are thus more appealing in digital applications. However, the chaotic behavior of digital chaotic systems gradually degenerates owing to the finite precision effect. Digital chaotic systems are not aperiodic but periodic [12–15].

Chaotic systems can also be classified into high-dimensional and low-dimensional systems. Low-dimensional chaotic systems have high efficiency and low resource consumption. The most commonly used low-dimensional systems are the logistic map [16], the Henon map [17], and the Sawtooth chaotic map [18–21]. The chaotic behavior of these systems is highly degenerate. It is difficult to ensure that the output sequence has a large period. By contrast, high-dimensional chaotic systems have a more complex nonlinear dynamic behavior. However, they have the disadvantages of high resource consumption and low-speed performance. Therefore, it is very necessary to design a large-period high-dimensional digital chaotic system with high-speed performance and low resource consumption.

Compared with other low-dimensional discrete chaotic systems, the Sawtooth chaotic map has a particularly simple form. It is easy to be digitized, as its output consists of positive decimals. There are several pseudo-random sequence generators based on the Sawtooth chaotic map. When the parameter satisfies a certain condition, the period of the output sequence can reach [22]. With parameter perturbations, the period can reach [23]. The variables and represent the precision length and the dimension, respectively. Although the period of the output sequence is large at the same precision, the operating efficiency is not satisfactory.

In this study, a digital pseudo-random sequence generator based on a high-dimensional discrete chaos map is proposed. For low computing complexity, the values of all the parameters of the high-dimensional discrete chaos are set as powers of two. Compared with the period of other digital chaotic pseudo-random sequence generators, the period of the output sequence of the proposed generator is closer to the upper limit of the maximum period.

2. Sawtooth Chaotic Map

The Sawtooth chaotic map is also called Bernoulli shift or Renyi map. It is defined as where and . It can be digitized by either fixed-point or float-point representation. Compared with floating-point computing, fixed-point computing is faster, and hardware implementation is smaller. Thus, for more efficient hardware implementation, fixed-point representation is chosen. For the decimal, the fixed-point representation of is where represents the integer part of . Therefore, (1) can be transformed into where is an integer. Multiplying both sides by , (3) is transformed into

The maximum period of the digital Sawtooth chaotic map (4) can reach for a certain parameter . There are two most commonly used parameters: one is 30517578125 (), and the other is 1220703125 (). The output sequence of the digital Sawtooth chaotic map consists of integers. They should be quantified as binary sequences before being tested by the NIST SP800-22 test suite. To ensure large periodicity, the quantified binary output sequences are the most significant bits (MSB) of the digital Sawtooth chaotic map output. When the parameter is 30517578125, the period of the output sequence can reach . The NIST SP800 test suite can reflect the statistical properties of the randomness of the pseudo-random sequence [24]. It consists of 15 different tests. Each test accepts as input a sequence of bits and returns a value. A sequence will pass the test if the corresponding value is greater than 0.01. The NIST SP800 test suite may also be used as follows: each test accepts as input sequences of bits. The test results contain two indicators: value and ratio. The ratio changes with . The value is the uniformity indicator of the value. If the value is greater than , the values are uniformly distributed. 100 output sequences of the digital Sawtooth chaotic map of length bits were tested by the NIST SP800 test suite, and the results are shown in Table 1.

The digital Sawtooth chaotic map fails the randomness test because the value of the nonoverlapping template is significantly less than . The resource consumption of the hardware implementation by FPGA (field-programmable gate array) is shown in Table 2, and the block diagram of the digital Sawtooth chaotic map in FPGA is shown in Figure 1.

3. Digital Pseudo-Random Sequence Generator

Although the randomness of the digital Sawtooth chaotic map is not satisfactory, its form is quite simple. Accordingly, a high-dimensional discrete chaotic system based on the Sawtooth chaotic map is proposed, and its digital model is analyzed in detail.

3.1. Fast Arithmetic Operation on Fixed-Point Computing

The arithmetic operations are multiplication, division, addition, and subtraction. Division is difficult to implement on FPGA; thus, it should be avoided in the formulation of the chaotic equation. The maximum frequency of FPGA is seriously affected by multiplication. In Table 2, the maximum frequency of the hardware implementation of the digital Sawtooth chaotic map by FPGA is not high for multiplication. For fast arithmetic operations in fixed-point computations, the values of all parameters are set as powers of two in this study. Therefore, division and multiplication are easier to implement. When the multiplier is a power of two, the function of is to shift bits of the multiplicand to the right, and the missing low position bits are filled by 0. When the divisor is a power of two, the function of is to shift bits of the dividend to the left, and the missing high position bits are filled by 0. The complex multiplication and division operations are thus reduced to the right and left shift operations, respectively. The shift operation is easier to implement on FPGA. Compared with subtraction, addition is easier to implement. Therefore, optimized multiplication, optimized division, and addition are selected in the design of the high-dimensional discrete chaotic system.

3.2. High-Dimensional Discrete Chaotic Map Modeling

By taking into account the form of the Sawtooth chaotic map, a high-dimensional discrete chaotic is proposed as follows: where is defined as a state vector , and is defined by

In (6), there are at most two nonzero elements per row to further reduce complexity and improve parallel computing efficiency. Therefore, the following parameter matrix is proposed: where , , and .

Proposition 1. When is odd, the value of the determinant of () is 1; when is even, .

Proof. Using the expansion theorem for determinants, . For and , . When is odd, ; when is even, .

Proposition 2. For the high-dimensional discrete map (5) and the parameter matrix (7), there exists at least one positive Lyapunov exponent in (5).

Proof. The Jacobian matrix of (5) is the parameter matrix (7). It is assumed that the eigenvalues of the parameter matrix are . By the fundamental property of the eigenvalues, . By Proposition 1, . There are two cases for the eigenvalues of the parameter matrix : either there exists at least a whose absolute value is greater than 1 or all eigenvalues are equal to 1. The latter is obviously impossible. Therefore, there exists at least one positive Lyapunov exponent in (5).

For at least one positive Lyapunov exponent in (5), the high-dimensional discrete map must be a chaotic system. In practical engineering, the dimension of the chaotic system need not be high. Therefore, a 6-dimensional discrete chaotic system is proposed in this study. The parameter matrix is defined by

Combined with (5), the 6-dimensional discrete chaotic system is represented by

Then, the six Lyapunov exponents are , , , , , and . Although (9) has only one positive Lyapunov exponent, the output sequence of its digital model has a large period. A discrete chaotic system with a large number of positive Lyapunov exponents does not ensure that the output sequence generated by its digital model will have a larger period. The phase diagram of the chaotic attractors is shown in Figure 2.

(a)

(b)

(c)

(d)

(e)

(f)

The variables , , , and are the delay signal of . Therefore, the phase diagrams (a), (b), and (c) are similar. Figure 3 shows the time series plots of the two sequences and generated by the map in (9), where , , , , , , and .

(a)

(b)

(c)

(d)

An autocorrelation algorithm can be used to detect the periodicity of the time series. It is defined as follows:

From Figure 3, it can be seen that the triangular wave is considerably smooth. This indicates that the output sequence is aperiodic.

Multistability is present in various chaotic systems. The parameter and the initial value seriously affect the stability of the chaotic system. In (5) and (9), the fixed parameter has no effect on stability. The Jacobian matrices of (5) and (9) are (7) and (8), respectively, which are constant matrices. Therefore, the Lyapunov exponents depend only on the constant matrices (7) and (8) and are the invariant constants. In (9), the six Lyapunov exponents are 0.3915, −0.0523, −0.0523, −0.0673, −0.1098, and −0.1098 for the initial value . For the positive Lyapunov exponent 0.3915, the discrete map (9) is a chaotic system. Propositions 1 and 2 prove that in (5), there exists at least one positive Lyapunov exponent. Therefore, (5) is also a chaotic system for all initial values.

3.3. High-Dimensional Digital Chaotic Map

Using (2) and (4), the high-dimensional digital chaotic map is defined as follows:

Equation (9) is transformed into where is in the interval . represents the integer part of . Although the Jacobian matrix of (12) is also (8), the value spaces of are limited. Therefore, (12) is periodic and can be described by the finite state machine in Figure 4.

The phase diagram of the attractors is also shown in Figure 5.

(a)

(b)

(c)

(d)

Compared with Figure 2, the phase diagram of the attractors shows a significant change: it is sparse because the value space of the variables is limited. In Figure 5, the attractors are obviously periodic; thus, the chaotic attractors degenerate into periodic attractors. Figure 6 shows the time series plots of the two sequences and generated by the map in (11), where , , , , , , and .

(a)

(b)

(c)

(d)

Compared with Figure 3, the triangular wave is not quite smooth and has a large number of sharp peaks. This indicates that the output sequence is not aperiodic. From Figures 6(a) and 6(c), it is obvious that the output sequence is periodic.

3.3.1. Period Analysis

Owing to the finite precision effect in the physical device, the chaotic behavior of the digital chaotic system gradually degenerates. The output sequences of the digital chaotic systems are all periodic. Therefore, a large period is an important indicator. For precision length , the maximum period of the output sequence of the 6-dimensional digital map is . The period of the output sequence of the digital chaotic system (12) for various values of is shown in Table 3.

From Table 3, it can be seen that the period of the output sequence generated by (12) increases sharply as increases. Compared with other high-dimensional map periods ( in [22] and in [23]), is significantly larger and closer to the maximum period. The initial values are selected as follows: , , , , , and . With computation precision 5, the period of the output sequence can reach 594621509 by using a 5-bit addition operation. It is efficient to generate a large period pseudo-random sequence with low resource consumption.

3.3.2. Quantification Analysis

The -bit fixed-point representation of is , , , and . The low position bits of , , are quantified as the output binary sequences. Therefore, more than one bit can be generated at a time. The throughput of the chaotic pseudo-random sequence generator can be significantly improved. Currently, SCMs (single-chip micyocos), ARMs (advanced RISC machines), CPUs, and FPGAs can process several bytes in one clock cycle, that is, 8 bits, 16 bits, 32 bits, and 64 bits. Therefore, quantification with several output bits is beneficial to information processing. However, it is unsafe to quantify all bits of as the output binary sequences. If the output sequences contain all the information of , can be easily predicted and reconstructed without prior knowledge of the initial seeds.

3.3.3. Quantity Analysis

The output sequences of (12) are , , , , , and . , , , , and are similar. Therefore, two different sequences can be generated by (12). A large number of new sequences can be generated by operations between and . In (12), there are three types of schemes for the output sequence: (a)The output sequence generated by .(b)The output sequence generated by .(c)The output sequence generated by operations between and , namely, and .

3.3.4. Randomness Analysis

100 sequences of length bits were tested by the NIST SP800 test suite, and the results are shown in Table 4. For comparison with Table 1, was set to 35.

The asterisk “” indicates that the corresponding test failed. From Tables 4 and 5, the randomness of the low position bits is better than that of high position bits. The randomness of the 8-bit outputs in and all passed the NIST SP800 test suit. This is due to the fact that the matrix involves the division . In fixed-point representations, when the divisor is a power of two, the function of is to shift bits of the dividend to the left, and the missing high position bits are filled by 0. Therefore, the low position bits are disturbed by the high position bits. As the missing high position bits are filled by 0, the disturbance of the high position bits is not significant. The test results for the output sequence generated by operations between and , are shown in Table 6.

By contrast, the randomness of the high position bits is better. The randomness of the output sequence generated by the addition operation “” is better compared with that by the xor operation “,” There are 27 different sequences in Table 6, and 17 different sequences passed the NIST SP800 test suit.

3.3.5. Performance Analysis

With the same and , the proposed pseudo-random sequence generator is faster than others because there are at most two nonzero elements per row in the parameter matrix , which ensures higher parallel performance in the hardware implementation. The resource consumption is shown in Table 7.

The consumption of memory bits and multiplier 9-bit elements is smaller, and the max frequency and throughput are higher compared with the corresponding values for the Sawtooth chaotic map. The block diagram of the 6-dimensional digital chaotic map in FPGA is shown in Figure 7.

3.3.6. Key Space Analysis

It is proved that the key space is sufficiently large to resist attacks by existing computers [25]. Therefore, the precision length need only be greater than 17 for (12). The key space changes with the precision length and the number of variables . The key space of (11) is .

3.3.7. Hardware and Software Parameter Selection

All the logic circuits in the hardware implementation used a single Altera Cyclone II family chip. The statistical analysis of the pseudo-random binary sequence was performed by the NIST SP800 test suite version 2.1.2 software package. In the parameter setting of NIST SP800, the block length for the block frequency test was 128, the block length for the nonoverlapping template test was 9, the block length of the overlapping template test was 9, the block length of the approximate rntropy test was 9, and the block length of the linear complexity test was 500.

4. Conclusion

The periodicity of the output sequence of a high-dimensional digital chaotic map is obviously larger than that of the output sequence of a low-dimensional digital chaotic map, and its randomness is also better. The proposed pseudo-random sequence generator based on a high-dimensional discrete chaotic map has parallel structure and lower hardware resource consumption, and its output sequence has a considerably large period. Moreover, the statistical performance of the proposed pseudo-random sequence generator was evaluated, and it was shown that it can pass all the tests in NIST SP8000 test suit.

Conflicts of Interest

The authors declare that there are no competing interests regarding the publication of this article.

Acknowledgments

This work is supported financially by National Natural Science Foundation of China (no. 61471158) and the Innovative Team of the Heilongjiang Province (no. 2012TD007).

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Copyright © 2018 Chuanfu Wang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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