Analysis of the Time Series Generated by a New High-Dimensional Discrete Chaotic System

Table 7

Performance of hardware implementation on FPGA.

Logic elements	Memory bits	Multiplier 9-bit elements	Max frequency	Throughput
				8 bits	16 bits	32 bits
119	66	0	177.62 MHz	1.387 G/s	2.775 G/s	5.550 G/s