| | Input: 64-bit known keystream KES and initial state candidates. |
| | Initialize clock counters: c2 = 0 and c3 = 0. |
| | Repeat for each instance of state candidate |
| | step1: computation based on majority rule |
| | if all three registers are clocked then compute REG2[20] using equation (5), increment counters c2++, c3++, and go to step2 |
| | else if registers REG1 and REG2 are clocked then compute REG2[20] using equation (6), increment counter c2++, and go to step3 |
| | else if registers REG2 and REG3 are clocked then compute REG2[20] using equation (7), increment c2++, c3++, and go to step2 |
| | else increase counter c3++, and go to step2 |
| | end if |
| | step2: |
| | if c3 < 8 then |
| | assign both possibility (i.e., 0 and 1) to REG3[20] and REG3[7] by replicating REG3 |
| | else if 8 ≤c3 < 10 then assign both possibility to REG3[20] by replicating REG3 |
| | end if |
| | step3: |
| | if clocking bit of REG2 is known and unknown for REG3 then make two replicas: copy 1: REG3[10] = 0; copy 2: REG3[10] = 1; |
| | else if clocking bit of REG3 is known and unknown for REG2 then make two replicas: |
| | copy 1: REG2[10] = 0; copy 2: REG2[10] = 1; |
| | else make four replicas: |
| | copy 1: REG2[10] = REG3[10] = 0; copy 2: REG2[10] = REG3[10] = 1; |
| | copy 3: REG2[10] = 0, REG3[10] = 1; copy 4: REG2[10] = 1, REG3[10] = 0; |
| | end if |
| | Until (c2 ≥ 10 and c3 ≥ 10) |
