Research Article
A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device
Figure 7
Effects analysis of the field plate profile: (a) TEM result of mini-LOCOS field plate profile; (b) effects of silicon loss on field plate lower profile through Hup/Hbottom; (c) effects of silicon loss on field plate lower profile through θ1 and θ2.
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