An Efficient RTL Design for a Wearable Brain–Computer Interface

Table 3

Latency of modules and proposed systems.

Modules and systems	Latency
Filter I	1 clk
Filter II	1  N clk
Filter III	(2 + order)  N clk
CSP	3  N clk
Variance	10 clk
SVM	1 clk
Prop. design I	12 + 3  N clk
Prop. design II	4  N + 11 clk
Prop. design III	(2 + order)  N + 3  N + 11 clk