Research Article
An Efficient RTL Design for a Wearable Brain–Computer Interface
Table 4
Comparison of different parameters of proposed designs and previous designs.
| | Data | Sampling rate (Hz) | Algorithms | Platform | Accuracy | Power (W) | Latency (ms) |
| [7] | MI, SSEVP, P300 | N/I | Adaptive filter, CSP, MD | Stratix-IV | 94.47 | 1.067 | 394 | [8] | MI | 256 | WOLA filter bank, CSP, MD | Stratix-IV | 80.2 | 0.67 | 430 | | | | Surface laplacian | | | | | [11] | MI | 128 | SCSSP, MI, LDA, SVM | Virtex-6 FPGA | 80.55 | 0.09 | 83 | [39] | SSEVP | 200 | FIR filter, averaging method | Cyclone II EP2C35 DSP | 90.62 | 27 | 2,000 | [40] | MI | 100 | CNN | ARM Cortex-M4 and M7 | 82.51 | 0.01 | 2.95 | Prop. design I | MI | 100 | IIR, CSP, VAR, SVM | Virtex-7 xcvu-65 FPGA | 77.45 | 0.026 | 0.13 | Prop. design II | MI | 100 | IIR, CSP, VAR, SVM | Virtex-7 xcvu-65 FPGA | 77.45 | 0.011 | 0.19 | Prop. design III | MI | 100 | IIR, CSP, VAR, SVM | Virtex-7 xcvu-65 FPGA | 77.45 | 0.011 | 0.63 |
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