An Efficient RTL Design for a Wearable Brain–Computer Interface

Table 6

Comparison of ASIC result.

	Power (W)	Area (mm^2)	Delay (ns)
Prop. design I	0.15	0.753124	2.37
Prop. design II	0.004	0.275067	2.27
Prop. design III	0.004	0.250889	2.27