Research Article
Accelerated and Highly Correlated ASIC Synthesis of AI Hardware Subsystems Using CGP
Figure 5
Distribution of gates in the evolved 5-bit circuits for power functions (x2, x3, and x4), with (a) showing circuits obtained using BwF, and (b) showing circuits using SL for different mutation rates. Similar distributions are observed for 2-bit to 4-bit circuits.
(a) |
(b) |