Design of a VLSI Decoder for Partially Structured LDPC Codes

Table 5

Comparisons with state-of-art decoders implementations.

	Previously published architectures			Proposed
	[26]	[27]	[28]
CN method	3-min	minsum	minsum	Ω
Precision	6 bit	8 bit	6 bit	8 bit
Technology	65 nm	130 nm	90 nm	130 nm
Frequency	400 MHz	83 MHz	109 MHz	400 MHz
Logic gates	520 kgates	420 kgates	380 kgates	564 kgates
Memory bits	500 kbits	106 kbits	100 kbits	544 kbits
Iterations	20	8	20	10
Net throughput	48 MBps	60 MBps	63 MBps	88 MBps
Normalized throughput	960 MBps	480 MBps	1260 MBps	880 MBps
TAR [5]	381	569	1620	321