Performance Analysis of a Reconfigurable Mixer Using Particle Swarm Optimization

Mehta, Shilpa; Li, Xue Jun; Donelli, Massimo

doi:https://doi.org/10.1155/2023/3786691

International Journal of RF and Microwave Computer-Aided Engineering

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Abstract Introduction Results Conclusion Data Availability Disclosure Conflicts of Interest Acknowledgments References Copyright Related Articles

Research Article | Open Access

Volume 2023 | Article ID 3786691 | https://doi.org/10.1155/2023/3786691

Performance Analysis of a Reconfigurable Mixer Using Particle Swarm Optimization

Shilpa Mehta,¹Xue Jun Li,¹and Massimo Donelli²

Academic Editor: Giovanni Crupi

Received01 Dec 2022

Revised03 Aug 2023

Accepted22 Aug 2023

Published20 Oct 2023

Abstract

In this article, a novel 1.8-5 GHz downconversion mixer is presented. The mixer is designed and simulated using SiGe 8HP 130 nm CMOS process technology. The proposed mixer is implemented by incorporating a double-balanced configuration, active inductor, and current mirror techniques. For performance optimization of the proposed mixer, different algorithms such as the genetic algorithm (GA), inclined plane system optimization (IPO) algorithm, and particle swarm optimization (PSO) algorithm have been used. Compared to existing works, this design shows an enhanced conversion gain (CG), a third-order input intercept point (IIP3), and return loss () at the expense of the noise figure (NF). Additionally, the design consumes low power and covers a small chip area compared to other state-of-the-art devices. PSO shows the most promising results when compared to other optimization algorithms’ results. According to the measurement results after PSO optimization, the mixer attains a maximum CG of 25 dB, an IIP3 of 4 dBm, and a NF of 5.2 dB at 5 GHz, while consuming only 15 mW of DC power. The mixer operates at 1.2 V and covers 0.8 mm² die area.

1. Introduction

With recent advances in the wireless industry, it is desirable to develop sophisticated receivers with reconfigurable components, which can be used to support a variety of wireless standards, significantly reducing development time and cost. Software-defined radios (SDRs) have proven to be a promising candidate that offers considerable flexibility by enabling various band operations within a single circuitry [1]. Mixers are one of the most critical components of SDRs.

Generally, mixers can be classified as passive mixers and active mixers [2]. Based on the design specifications, any of these mixer topologies can be used. For example, passive mixers maintain high linearity and good noise figure (NF) performance at the expense of port isolation. Likewise, the port isolation problem can be overcome by active mixers. Moreover, these mixers can provide high conversion gain (CG) and low NF at the expense of linearity. Gilbert mixers are one of the common types of active mixers that are widely used in RF circuits [3–5]. These mixers are adopted in SDR receivers due to their broadband operation and wideband coverage [6]. However, because of the parasitic capacitance at different nodes, these mixers are not suitable for high-frequency applications. To address this issue, folded structures can be utilized due to less number of transistor requirements; however, they consume high power. Different techniques can be used to enhance the performance of a mixer, of which current bleeding appears promising.

Several mixers were reported in the literature based on the current bleeding approach that integrated inductive degeneration [7], forward body, inductive gate bias, inductive resonance [8], and gm/ID [8] techniques to improve the overall performance of the proposed mixers. However, the proposed mixers were not able to maintain high linearity. Therefore, based on literature studies, various promising techniques have been identified that are capable of improving linearity performance, such as resistive degeneration [9] and derivative superposition [10]. In [11], an improved derivative superposition technique is used to enhance the linearity performance of the mixer. Current bleeding and current reuse techniques are also used to enhance CG and NF performance. The proposed mixer not only consumed less power but also small chip area. Another mixer based on source degeneration and current bleeding with a resistive load approach is proposed in [12]. The proposed mixer consumed less power and attained reasonable CG and high IIP3 at the expense of NF. To further enhance the NF and CG performance, another mixer based on the conventional Gilbert mixer is proposed [13]. The proposed mixer employed a differential active inductor (DAI) circuit, a cross-coupled current injection technique, and cross-coupled current bleeding techniques to improve flicker noise and CG performance. Active inductor circuitry resonates with parasitic components, thus lowering the leakage current that contains harmonic components and generating flicker noise [14]. Finally, a high IIP3 and low NF mixer based on active load, cross-connected design topology, and current bleeding technique are proposed [15]. The proposed mixer is well suited for wireless local area network applications. However, the above proposed designs involve many tradeoffs among CG, NF, IIP3, and power consumption, resulting in a more complicated design [16–19]. Moreover, sizing circuits to meet specific performance specifications is an intricate and time-consuming process. Nowadays, researchers are primarily concerned with space limitations and economic factors. Designers perform several functional experiments using computer simulations and design software in order to meet these requirements. Manual adjustment of the tunable parameters is a time-consuming task. Therefore, researchers have attempted to employ optimization algorithms to optimize the circuit parameters [20, 21]. Genetic algorithm (GA) [22], inclined plane system optimization (IPO) algorithm [20], and particle swarm optimization (PSO) are some of the commonly used algorithms to solve the multiobjective problems where CG, NF, and IIP3 are the objectives or parameters to be optimized [23, 24]. The implementation of these algorithms has been described in several studies by researchers, but no work has been identified that shows the implementation of these algorithms on mixers. Thus, to the best of our knowledge, our work is the first to demonstrate such implementation on a mixer.

In this work, a novel double-balanced mixer was proposed with the objective of achieving high CG and good IIP3 and an active inductor technique was found to be the most efficient method to achieve these objectives. Based on this, an active inductor circuit is employed instead of passive inductors within the circuit. In addition, a triple transistor current mirror circuit is used instead of a conventional current mirror circuit to control the overall current within the circuit. Moreover, due to the limitations of the Gilbert mixer, the proposed design uses mixing stages based on single transistors, resulting in a small chip area. GA, IPO, and PSO have been used to optimize mixer performance using an equation-based approach using MATLAB. The proposed mixer is designed and simulated in SiGe 8HP 130 nm CMOS process technology to validate that the optimization-based design is satisfying the desired specifications. The remainder of the paper is organized as follows. Section 2 discusses the proposed mixer design, and Section 3 presents the analysis of the design. Section 4 describes optimization algorithms, and the results of the proposed design are discussed in Section 5, and finally, Section 6 concludes the paper.

2. Proposed Mixer

Figure 1 shows the design of the proposed balanced mixer. The mixer consists of a mixing stage, improved current mirror stage, and active inductor stage, respectively.

2.1. Current Mirror

Circuits that mirror current are constructed using two main transistors, which reflect current that flows through one transistor and flows through the other. Depending on the circuit requirements, the copied current can be constant or variable [25]. The proposed mixer’s current mirror stage consists of transistors (T₀, T₁, T₆, T₇, and T₈) responsible for controlling the current within the circuitry. Similarly, to maintain symmetry within the circuit, another current mirror circuit consists of transistors (T₉-T₁₃). All transistors operate in the saturation region. Transistors T₇ and T₁₀ are responsible for mirroring the current within the transistors T₈ and T₉. This current will be mirrored to the transistors T₀ and T₁₂ which are responsible for providing the current to the transistors T₁ or T₁₁. Transistors T₁ or T₁₁ also receive current from the transistors T₆ or T₁₃ so that sufficient current is maintained within the mixing stage transistors T₃ and T₄, respectively.

2.2. Mixing Stage

The mixing stage consists of n-type field effect transistors (NFETs) (T₃, T₄). According to the design, RF+/RF- and LO+/LO- inputs are imparted through the gate and source terminals. Likewise, IF+/IF- outputs are obtained at the drain terminals.

Due to their tightly controlled physical sizes, resistors are difficult to fabricate, which makes transistors an optimal choice at the load instead of resistors. Further, high CG requires large drain resistors, resulting in a lower DC biasing voltage required at the output port. As a result, transistor operating conditions may be affected. Thus, using transistors (T₂ and T₅) at the load, the current increases within the mixing stage to such an extent that T₃ and T₄ operate in the saturation region and result in minimal flicker noise. Consequently, this improves the transconductance and hence the overall CG.

2.3. Differential Active Inductor

There are a variety of passive electronic components available in complementary metal-oxide semiconductor- (CMOS) based process technologies, including bond wires, spirals, multilevel spirals, and solenoids [26]. The choice of inductors varies with the application.

Spiral-layout inductors are commonly used in signal processing and data communication applications. They have degraded performance because their spiral layout structure requires large silicon areas, causing a low-quality factor and low self-resonance frequency. Therefore, active inductors are typically employed in circuits. Various active devices are used to develop these inductors, including metal-oxide-semiconductor field effect transistors (MOSFETs), operational amplifiers (Op-Amps), operational transconductance amplifiers (OTAs), and resistors [27]. Inductors are usually used in conjunction with resistors as feedback elements, which ultimately improve the overall performance of active inductors. Alternatively, inductors can be used in a gyrator C topology, which contains two transconductors arranged in a feedback configuration. As long as DC bias conditions and signal swing restrictions are met, an actively biased network (a combination of active devices) behaves as an inductor within a specific frequency band [28]. These inductors have high tunability and quality factors, making them suitable for low amplifiers and mixers as differential RF front-ends.

High linearity is also desired in SDR mixers while maintaining reasonable CG at the expense of NF, which can be achieved by using an active inductor across the IF stage of the design. The active inductor circuit topology is useful within the mixer circuitry to tune out parasitic capacitors and thus reduce flicker noise [13]. Various active inductor topologies are discussed in [29, 30]. We propose a mixer that uses a differential active inductor with current mirror circuitry. Cascode reduces output conductance and boosts gain at high frequencies using this technique. Dual gain stages were incorporated within this stage to maximize the cascode effect. The transistors (T₂₀-T₂₂, T₂₆) operate in saturation region. Moreover, transistors (T₂₁-T₂₂) are biased in the triode region that behave as voltage-controlled resistors. The bias voltages of these transistors are varied to show the tunability behavior of the inductor. The cross-coupled transistors are balanced with the other transistors, i.e., (T₁₉ and T₂₃) and (T₁₈ and T₂₄), respectively. Transistors T₁₄ and T₂₇ are diode loads. Moreover, transistors (T₁₅-T₁₆) and (T₂₈-T₂₉) deliver current to the next stages.

A current mirror circuit controls the current in the active inductor by mirroring the current from current mirror stages from the left- and right-hand sides of the active inductor to transistors (T₁₇ and T₂₅), respectively. RL equivalent circuit is used to simplify the active inductor circuitry as shown in Figure 2 [31]. The expressions for the RL circuit are defined as follows: where , , , and are transconductance of transistors T₁₅, T₁₇, T₁₈, and T₂₃. is very small due to the second-order effect. To obtain the resonant frequency (), is neglected, which is given by where for transistors at resonant frequency. Thus, , , , and correspond to transistors T₁₅, T₁₈, T₁₉, and T₂₃.

To determine the broadband characteristics of the active inductors, it is necessary to calculate the quality factor ( factor), which can be approximated by the following expression:

3. Performance Analysis

3.1. Conversion Gain

Figure 3 shows the complete small signal model for the proposed mixer circuit for CG analysis. The load and current mirror sections are simply represented as resistors (, ). Furthermore, the active inductor is defined using an equivalent RL circuit as shown Figure 2. Thus, the complete circuit behaves like a common source amplifier with a source-degeneration resistor. Based on the circuit shown in Figure 3, the controlled current source determines the current through . Voltage, can be expressed as Gain, can be expressed as

Once is obtained, the output voltage, can be expressed as where .

Substituting from (5) to (6), we get where .

To determine the impact of parasitic capacitors, and , Miller’s theorem can be used, which relates the equivalent capacitance to the gain between the nodes to which the capacitor is connected. Assume that , , and are present at the gate, source, and drain terminals of the transistor T₃. Thus, these capacitances can be expressed by Miller’s theorem as

3.2. Noise Figure

To determine noise performance, the low-frequency noise of all proposed circuitry components is modeled using noise voltage sources [32, 33]. The first step is to determine the gain from each noise source to the output node, i.e., .

The gain from and is expressed as where denotes the output impedance at node 0. Furthermore, the gain from and is defined as

Using the gain factors obtained in (10) and (11), the output noise value can be expressed as

The obtained output noise can be related back to input noise by dividing it by the obtained gain as mentioned in (8). Thus, it is expressed as where and refer to the power spectral density of transistors T₂ and T₃.

3.3. Linearity

It is essential to determine the nonlinear behavior of the mixer circuit. Based on the literature study, we found that resonant circuits are capable of enhancing linearity performance. As per conventional Gilbert mixers, harmonic generation is possible, especially due to the RF stage, because the LO stage behaves like a switch and the load stage contains passive components. Thus, the LO and load stages do not produce distortions [34]. Within the transconductance stage, the main sources of harmonics are transconductance (), output conductance (), and gate-source capacitance (), where is the most predominant one. Thus, the equivalent drain current of the transconductance stage is represented as a function of and where the coefficients , , and represent the transconductance, order, and order nonlinearity of transistor transconductance, respectively. Additionally, and refer to the gate and source voltages of the transistor. In addition, switching-stage transistors are responsible for providing parasitic components, which results in linearity degradation. Based on the above discussion, it has been found that the harmonics of the mixer depend on all transistors present within the design and parasitic component effects.

In the proposed design, a single transistor works as a mixer; therefore, the parasitic effect and are equally important for the main mixer transistors, i.e., T₃ and T₄. Furthermore, the load stage also contains transistors instead of passive components, and parasitics obtained using T₃ and T₄ are balanced using the active inductor circuit.

Additionally, the circuit also includes current mirror circuits with resistive loads where the parasitic effect can be considered. Thus, the drain current through the main transistor T₃ will be dependent on load and active inductor stage transistors as well. Additionally, the harmonics will be dependent on all the transistors T₀-T₃₉ within the proposed circuit. where and refer to current flowing through load and active inductor stages, respectively.

Based on the small signal model shown in Figure 3, the total current flow through the half-mixer circuit is expressed in equation (15). Furthermore, the parasitic capacitance at node is denoted by which is balanced by the active inductor circuitry. According to equation (15), the transconductance of the half-mixer is expressed as where , , and refer to the transconductance of the mixing stage, load stage, and active inductor stage transistors, respectively.

3.4. Power Consumption

In general, power consumption is expressed as DC current () times supply voltage. where and refer to DC current and supply voltage, respectively.

The proposed mixer must be able to provide high CG and good IIP3 at the expense of NF throughout the entire band of operation. Therefore, to maintain good performance, design optimization, good wideband matching, and other desired parameters must be taken into account.

4. Optimization Algorithms

Today’s commercial CAD tools can only solve simulation tasks, not automatic schematic generation. With these tools, it is impossible to control circuit configurations and all design performances accurately.

The design process is time-consuming and challenging; it requires a highly skilled individual to execute it. As a result, optimizing algorithms become essential for solving such problems [35]. In the literature, different algorithms are described, such as genetic algorithm (GA), particle swarm optimization (PSO), and inclined plane system optimization (IPO) algorithms, that have been successful when implemented on analog circuits including operational amplifiers, low noise amplifiers (LNAs), and filters. However, we believe that our work is the first one to demonstrate the implementation of these algorithms on mixer circuits.

This section discusses all of these algorithms and the process of implementing them on the mixer circuits. Despite the differences in the implementation process, all these algorithms are aimed at improving the mixer’s performance. Therefore, the algorithms are implemented one by one to see how well the proposed mixer performs under different optimizations and, additionally, how optimized results are better than unoptimized results.

The whole process is briefly explained as follows: (a) develop a high-performance reconfigurable mixer, (b) simulate using SiGe 8HP 130 nm CMOS process technology (with no optimization), and (c) implement optimization algorithms under different conditions and requirements as per algorithms and the proposed mixer. Thus, if desired conditions are met and requirements are fulfilled, then the process is completed. Otherwise, it is iterated until desired results are obtained: (d) comparison and identification of the best optimization algorithm based on the obtained results and (e) comparison of optimized and unoptimized results.

The following is a step-by-step explanation of each algorithm’s implementation.

4.1. Genetic Algorithm

In the genetic algorithm (GA), optimum parameters for a problem are obtained by following the natural evolution process. Additionally, GA works well with complex and nonlinear systems [22].

4.1.1. GA Implementation on Proposed Mixer

In this work, GA is used as a search algorithm for the optimization of various performance parameters such as CG, Pdiss, IIP3, , , and NF, respectively. Thus, minimization and maximization of these parameters are dependent on the values of various variables such as of transistors, , , , , and of the proposed mixer. The implementation of this algorithm is done in MATLAB to obtain the optimized values of the desired variables and subsequently satisfy the performance and specifications for the proposed design. Figure 4 depicts the flow chart which highlights the GA procedure utilized to achieve the required performance.

To start the process, the chromosome is designed to contain the variables specified above, followed by random population creation of this chromosome. Each part of this chromosome is referred to as a gene (the real value of each variable). The real value is then converted into binary code of varied and proper length.

When parameter values of the design differ in scale, adjusting the length of binary codes depends on the desired precision and range of each variable [22]. The desired values and range are as follows: (a) () , (b) () , (c), (d) V, and (e) mA; GA operators are given by (a) crossover rate (), (b) mutation rate (), and (c) number of .

Following this, the fitness or objective function of each chromosome is obtained. As the fitness function is evaluated for more than one objective function, it is expressed as where is the object and is the required value of an object. Likewise, refers to the number of objects and denotes the weight coefficients of object. Thus, the fitness function for the proposed mixer is expressed as where refer to weights corresponding to performance parameters, i.e., , IIP3, frequency (), NF, Pdiss, and , respectively. Weights are selected between 50 μm and 650 μm in accordance with work presented in the literature that employs a genetic algorithm to enhance overall performance. In addition, these values are most suitable for achieving the circuit’s performance objectives [22]. All expressions defined in Section 3 are used for overall estimation. Once all conditions of the objective function are satisfied, the optimum results are obtained. The required information of parameters and their specified range is available in chromosomes being realized by genes that correspond to the desired variables for the proposed design. The obtained results are compared with the simulation results obtained before applying this algorithm. The optimized results are later compared with the results obtained from other algorithms as well.

4.2. Inclined Plane System Optimization

The inclined plane system technique is characterized by spherical objects such as balls that interact on a nonrigid, sloping surface to reach the bottom point. In this algorithm, height values are assigned to reference points for each ball based on a fitness function where potential energy is calculated at various elevations by estimating these height values. When these balls fall, their energy is converted to kinetic energy, accelerating them downward. In this way, balls begin to lose their potential energy and reach their minimum point.

In the search space, each ball is described by three coordinates: its position, its height, and its angle with other balls. The th position of each ball is defined as where refers to th ball position within -dimension in the -dimensional space.

Position of th ball is defined below: where refers to the height of the th ball.

Additionally, the acceleration of the ball due to inclined planes can be expressed as

Likewise, acceleration within -dimensional and time, is expressed as

Position update for the ball is possible using equation (22) as below: where and refer to random constants obtained with a range of [0,1] and and refer to the control functions which are expressed as where , , and are all constants. where , , and are all constants.

Finally, the speed of each ball is expressed as where corresponds to the ball with the lowest height.

Figure 5 depicts the flow chart which highlights the IPO procedure utilized to achieve the required performance. The following are the steps that are followed to perform this optimization: (a) The population is created randomly based on the predetermined range. (b) Population fitness (height) is determined. (c) Best balls are recorded in the external storage (record positions). (d) Every ball’s position is updated; that is, all nondominant balls are placed in storage. Thus, if storage reaches a certain limit, supercubes can be created where balls can be stored according to their coordinates. (e) The supercubes with the highest number of balls are identified, and unnecessary points are randomly deleted to reduce storage capacity [20].

4.3. IPO Implementation on Proposed Mixer

For the proposed mixer, initial simulations are done in Cadence software and the results are obtained. Later, IPO is implemented to optimize the proposed mixer.

The cost function is provided below:

Figure 6 depicts the flow chart which depicts the IPO implementation procedure, and the steps are enlisted as follows: (a) IPO implementation; (b) setting maximum iterations (Max-It) to 100 and number of balls () to 30 for IPO, which is considered as an initial population; (c) the input parameters were extracted from the IPO and substituted in Cadence for subsequent simulations; and (d) all fitness functions are called by MATLAB. Once the best members have been identified, they are stored in an external list. The process continues till conditions are met. This optimization has improved the mixer’s performance over that obtained using prior algorithms.

4.4. Particle Swarm Optimization

The technique is based on the behaviors of several insects and animals that cooperate in a swarm, including bees, ants, fish, and birds [24]. The vectors and represent the positions and velocity of the agents, respectively. By iterating the velocity (30) and position update equations (31) reported below, the modified position of the agent is realized. where refers to the -agent velocity at -iteration, is the weighting function, and are the acceleration coefficients, rand is a random number generator between 0 and 1, is the current position of the -agent at iteration, is the pbest of agent , and gbest is the global best of the group. Likewise, the position of each agent is expressed as

The objective function is also optimized in this process, where all agents know their best value (pbest), their and positions, and the best value for a group (gbest) among the pbest values.

4.5. PSO Implementation on the Proposed Mixer: Specifications and Objectives

The proposed mixer has been designed based on PSO with an objective function as maximization of the figure of merit (FOM) of the proposed mixer. Thus, the cost function is expressed as where IIP3, , BW, NF, , and Pdiss are linearity in dBm, gain in dB, BW in GHz, noise figure in dB, return loss in dB, and power dissipation in mW, respectively. It is, therefore, necessary to increase CG and IIP3 and reduce NF and power dissipation in order to maximize the objective function. An equation-based approach has been used to optimize the proposed mixer, and all the obtained expressions have been specified in Section 3.

The PSO has been implemented using MATLAB, and all the design specifications for the mixer design are as follows: (a) supply V, (b) dB, (c) dB, and (d) dBm. Similarly, the PSO specifications are given by (a) swarm , (b) , (c) , and (d) . The design variables for the proposed mixer are defined as (a) () , (b) () , (c) , and (d) V.

The design reconfiguration is based on the variation in the bias voltage corresponding to the transistors T₂₁-T₂₂. Thus, maximum power is transferred when the active inductor is fully matched with the parasitic capacitances at the IF end of the main transistors T₃-T₄. The aspect ratio () is achieved upon obtaining the , , and values using basic transistor equations where mobility, gate oxide capacitance, and threshold voltage are based on 8HP CMOS process technology. Furthermore, the linearity of the mixer is highly dependent on the operating conditions of the main transistors T₃ and T₄, respectively. To attain the optimal values of CG, NF, and IIP3, the equations are represented in equations (8), (13), and (15), respectively [44].

Figure 6 depicts the flow chart which depicts the PSO implementation procedure, and the steps are enlisted as follows: (a) PSO implementation, (b) extract input parameters from PSO and replace them in Cadence, (c) run Cadence and resimulate, and (d) all fitness functions are called by MATLAB. Once the best members have been identified, they are stored in an external list. The process continues till conditions are met. This optimization has improved the mixer’s performance over that obtained using prior algorithms. The optimization and measurement results are discussed in the next section.

5. Results and Discussions

The proposed mixer has been designed and fabricated using SiGe 8HP 130 nm CMOS process technology. For simulation purposes, the supply voltage is set to 1.2 V. Upon simulating the design in Cadence software, it has been found that the maximum CG reached by the design is 26 dB and IIP3 is 4 dBm. Similarly, the minimum NF at the maximum frequency is 5.3 dB. Simulation results demonstrate the validity of the mathematical models for CG, NF, and IIP3. Figure 7 depicts the comparison of CG performance upon implementation of GA, IPO, and PSO algorithms. From the plots, it has been found that the proposed mixer attained a maximum CG (after PSO) of 26 dB upon simulation, which lowered to 25 dB upon measurement. Likewise, for IPO and GA, the maximum CG are 23.5 dB and 22.5 dB, respectively. Based on the observation, it has been found that the proposed mixer attains the best results when optimized with PSO. Figure 8 depicts the comparison of NF performance upon implementation of GA, IPO, and PSO algorithms. The mixer exhibits a measured NF of 7.8 dB at 1.8 GHz and drops to 5.3 dB at 5 GHz. The simulated NF (after PSO), on the other hand, ranges from 5.3 to 7.8 dB as shown in Figure 8. Similarly, for IPO and GA, NF is within the range of (5.4-7.7)dB and (5.6-7.9)dB, respectively. Based on the observation, it has been found that the proposed mixer attains the best results when optimized with PSO in terms of NF. Variation can be observed in the simulated and measured results, due to inaccuracy of the transistors, parasitic capacitance effect, and use of external baluns. The proposed design is also fabricated and tested. The chip die microphotograph is shown in Figure 9 which covers an area of 0.8 mm². For chip evaluation purposes, external baluns were used with an input-matching network present at the RF and LO ports, respectively. Additionally, an output buffer of 0 dB gain was also used. On wafer, measurements were made while fixing the LO frequency of 2 GHz for proposed mixer’s performance measurement purposes. Thus, with the variation in the RF frequency from 1.8-5 GHz, the measured return loss () PSO was plotted as shown in Figure 10. Upon observation, it has been found that the simulated and measured are better than 10 dB within the entire band of operation. Likewise, results for after IPO and GA optimization are shown in Figures 11 and 12. Additionally, the mixer operates at 1.2 V while consuming a low power of 15 mW while maintaining an IIP3 of 4 dBm (after PSO), as shown in Figure 13. Table 1 depicts the performance comparison summary of the proposed mixer (with and without optimization) with the other works reported in the literature which employed active inductor technique within their proposed circuit. Upon comparison, it has been noticed that the proposed mixer attains good CG and reasonable IIP3 while covering a small area but at the expense of NF.

6. Conclusion

This paper proposes a novel reconfigurable downconversion mixer. The use of an active inductor at the load end of the main mixing transistors is the mechanism used to maintain a high gain while improving the linearity. PSO, IPO, and GA have been used to optimize the proposed mixer. Upon optimization and comparison, the best results have been obtained when optimized using PSO. The measurement results after PSO implementation showed a conversion gain of 25 dB, as well as an IIP3 of 4 dBm at the expense of NF of 5.2 dB.

Data Availability

The article contains all the data

Disclosure

A part of this study has been presented in PhD thesis (https://openrepository.aut.ac.nz/server/api/core/bitstreams/5a18 331a-475f-87a2-40f1c43f6fb9/content).

Conflicts of Interest

The authors declare no conflict of interest.

Acknowledgments

The authors would like to thank Auckland University of Technology for providing them with opportunities to conduct research and contributions to this study. Open access publishing was facilitated by Auckland University of Technology, as part of the Wiley-Auckland University of Technology agreement via the Council of Australian University Librarians.

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Copyright © 2023 Shilpa Mehta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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