Optimally Matched 189-232 GHz 6.8 dBm Output Power CMOS Frequency Doubler

<div>Simulated output power of the doubler versus gate bias at 220 GHz. Load-pull simulation at <svg height="11.9283pt" id="M11" style="vertical-align:-3.40332pt" version="1.1" viewbox="-0.0498162 -8.52498 51.2032 11.9283" width="51.2032pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M687 650H462V622C543 612 549 605 530 547C498 447 422 252 372 126H370C302 298 229 492 204 563C188 607 191 615 262 622V650H17V622C77 616 93 608 122 534C180 389 262 172 329 -11H360C436 196 541 450 568 516C606 605 619 614 687 622V650Z"></path></g><g transform="matrix(.013,0,0,-0.013,7.638,0)"><path d="M463 437C426 431 375 425 327 422C297 440 264 449 231 449H230C153 449 51 396 51 283C51 215 94 168 139 149C123 129 91 103 51 88C50 78 53 60 62 46C75 25 100 2 136 -9C112 -28 73 -59 53 -79C38 -94 29 -113 29 -135C30 -192 91 -257 203 -257C336 -257 452 -160 452 -59C452 39 371 59 309 59C275 59 240 58 203 58C158 58 140 77 140 96C140 110 157 129 170 138C186 135 205 133 221 133C306 133 396 185 396 293C396 328 384 360 366 381L423 378C439 387 459 413 468 429L463 437ZM219 418C277 418 314 362 314 284C314 205 275 166 231 165C176 165 137 221 137 299C137 376 177 418 219 418ZM241 -11C285 -11 314 -14 339 -24C367 -36 384 -61 384 -95C384 -157 335 -206 240 -206C166 -206 108 -165 108 -110C108 -82 128 -54 154 -32C172 -17 195 -11 241 -11Z"></path></g><g transform="matrix(.013,0,0,-0.013,13.722,0)"><path d="M319 325C317 349 306 409 297 431C277 440 250 449 209 449C117 449 57 389 57 319C57 243 122 209 182 182C232 159 261 135 261 91C261 48 227 21 190 21C130 21 85 79 68 145L41 140C41 104 51 36 58 22C75 7 121 -12 172 -12C252 -12 337 35 337 126C337 195 286 231 210 262C166 281 126 304 126 348C126 388 152 417 191 417C240 417 274 378 294 318L319 325Z"></path></g><g transform="matrix(.013,0,0,-0.013,22.2,0)"><path d="M535 323V373H52V323H535ZM535 138V188H52V138H535Z"></path></g><g transform="matrix(.013,0,0,-0.013,33.463,0)"><path d="M241 635C89 635 35 457 35 312C35 153 89 -12 240 -12C390 -12 443 166 443 312C443 466 390 635 241 635ZM238 602C329 602 354 454 354 312C354 172 330 22 240 22C152 22 124 173 124 313S148 602 238 602Z"></path></g><g transform="matrix(.013,0,0,-0.013,41.878,0)"><path d="M687 650H462V622C543 612 549 605 530 547C498 447 422 252 372 126H370C302 298 229 492 204 563C188 607 191 615 262 622V650H17V622C77 616 93 608 122 534C180 389 262 172 329 -11H360C436 196 541 450 568 516C606 605 619 614 687 622V650Z"></path></g></svg> is demonstrated in the inset.</div>

International Journal of RF and Microwave Computer-Aided Engineering

fig4

Figure 4

Figure 4: Optimally Matched 189-232 GHz 6.8 dBm Output Power CMOS Frequency Doubler 