Research Article
Exploration of Heterogeneous FPGA Architectures
Table 1
DSP benchmarks set I.
| | Circuit name | Inputs | Outputs | CLBs (LUT4) | Mult () | Slansky () | Sff (8) | Sub () | Smux (32 : 16) |
| | ADAC | 18 | 16 | 47 | — | — | 2 | — | 1 | | DCU | 35 | 16 | 34 | 1 | 1 | 4 | 2 | 2 | | FIR | 9 | 16 | 32 | 4 | 3 | 4 | — | — | | FFT | 48 | 64 | 94 | 4 | 3 | — | 6 | — |
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