AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC
Figure 10
Results for the different configurations explored with AADL descriptions of a specific FPGA circuit and a set of tasks. As previously mentioned, Conf1 and Conf8 are incorrect due to their total execution time or total area.
(a) The global area needed for each configuration
(b) The global energy consumed for each configuration
