A High-Speed Dynamic Partial Reconfiguration Controller Using Direct Memory Access Through a Multiport Memory Controller and Overclocking with Active Feedback

Table 1

Existing Dynamic Partial Reconfiguration Approaches.

Study	Device, bitstr. mem.	Method	Max ICAP speed
Claus et al.; [4], 2008	Virtex-2P, DDR	OPB	4.77 MB/s @100 MHz
Claus et al.; [4], 2008	Virtex-2P, DDR	PLB bus Custom ICAP DMA contr.	89.9 MB/s @100 MHz
Bomel at al.; [6], 2009	Virtex-2P, DDR	Ethernet	50 MB/s @100 MHz
Claus et al.; [4], 2008	Virtex-4, DDR2	OPB	5.07 MB/s @100 MHz
Claus et al.; [4], 2008	Virtex-4, DDR2	PLB bus Custom ICAP DMA contr.	295.4 MB/s @100 MHz
Manet et al.; [5], 2008	Virtex-4, ZBT SRAM or DDR	Custom ICAP DMA contr.	350 MB/s @100 MHz
shelburne et al. [7], 2010	Virtex-4, FPGA BRAM	MetaWire (custom)	219.31 MB/s @100 MHz
Bomel et al.; [6], 2009	Virtex-4, DDR	Ethernet	50 MB/s @100 MHz
Liu et al.; [8], 2010	Virtex-4, FPGA BRAM	PLB IP for BRAM Tx (fastest)	371.4 MB/s (max) @100 MHz