An NoC Traffic Compiler for Efficient FPGA Implementation of Sparse Graph-Oriented Workloads

Table 2

NoC timing model.

Mesh Switch	Latency
𝑇through (X-X, Y-Y)	2
𝑇turn (X-Y, X-Y)	4
𝑇interface (PE-NoC, NoC-PE)	6
𝑇wire (GraphStep NoC)	2
𝑇wire (Token Dataflow NoC)	5
Processing Element	Latency
𝑇send	1
𝑇receive (ConceptNet, Bellman-Ford)	1
𝑇receive (Matrix-Vector Multiply)	9
𝑇add (Sparse Matrix Solve)	8
𝑇multiply (Sparse Matrix Solve)	10
𝑇divide (Sparse Matrix Solve)	57