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International Journal of Reconfigurable Computing
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International Journal of Reconfigurable Computing
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2011
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Article
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Tab 6
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Research Article
Reduced-Precision Redundancy on FPGAs
Table 6
Number of SEUs causing each class of effect for an FIR filter protected with TMR and several levels of RPR using experimentally determined thresholds (
), compared to the unmitigated filter.
Design
Slices used
Slices overhead
Class 1 bits
Class 2bits
Class 3bits
Class 4 bits
Total utilized bits
Total catastrophic (% reduction)
Improv. in failure rate
Unmitigated
1,030
—
59,156
6,472
1,501
943
68,072
2,444 (—%)
—
TMR
3,171
208%
218,304
0
0
2
218,306
2 (99.9%)
1222×
RPR,
1,755
70.4%
106,863
6,191
11
2
113,067
13 (99.5%)
188×
RPR,
1,602
55.5%
95,980
7,731
9
2
103,722
11 (99.6%)
222×
RPR,
1,470
42.7%
84,583
7,709
42
2
92,336
44 (98.2%)
55.5×
RPR,
1,394
35.3%
79,334
8,252
254
2
87,842
256 (89.5%)
9.55×
RPR,
1,313
27.5%
74,129
8,267
634
36
83,066
670 (72.6%)
3.65×