Research Article
A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance
Table 2
Small configuration results.
| | Arch. |
App. | Small Cfg.: 1 tile, PEs each tile | | Ops | Cycles | Avg. IPC | Perf. Gain | Efficiency |
| | RCP | idct(row+col) | — | — | 9.2 | — | 57% | | FDR-CGRA | idct(row+col) | 2042 | 184 | 11.1 | 21% | 69% |
| | FDR-CGRA | interpolate_avg4_c | 1193 | 136 | 8.8 | — | 55% | | FDR-CGRA | interpolate_halfpel__c | 1295 | 135 | 9.6 | — | 60% | | FDR-CGRA | sad16_c() | 3441 | 339 | 10.2 | — | 63% |
| | ADRES | get_blocks (64 PEs) | — | — | 29.9(64 PEs) | — | 47% | | FDR-CGRA | get_block(H) | 340 | 38 | 8.9 | — | 56% | | FDR-CGRA | get_block(V) | 296 | 37 | 8.0 | — | 50% | | FDR-CGRA | get_block(V+H) | 899 | 93 | 9.7 | — | 60% | | FDR-CGRA | get_block(H+V) | 900 | 95 | 9.5 | — | 59% | | FDR-CGRA | Adjusted Avg. (4 tiles) | — | — | 36.1(4 tiles) | 21% | 56% |
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