A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection

<table class="table-group" id="tab6"><tr><td><table class="table"><tr><td class="thead-hr" colspan="3"><hr/></td></tr><tr><td align="left">VEH</td><td align="center">  LUT</td><td align="center">  Reg. Bits </td></tr><tr><td align="center" colspan="3"><hr/></td></tr><tr><td align="left"> SIP 128 Bit</td><td align="center"> 1082</td><td align="center"> 358</td></tr><tr><td align="left">SIP 64 Bit</td><td align="center"> 619</td><td align="center"> 278 </td></tr><tr><td align="center" colspan="3"><hr/></td></tr><tr><td align="left"> Web Server 128 Bit</td><td align="center"> 1026</td><td align="center"> 586</td></tr><tr><td align="left">Web Server 64 Bit</td><td align="center"> 663</td><td align="center"> 244</td></tr><tr class="table-tr"><td colspan="3"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Synthesis results for 128 b and 64 b VEHs. 

International Journal of Reconfigurable Computing

tab6

Table 6

Table 6: A Dynamically Reconfigured Multi-FPGA Network Platform for High-Speed Malware Collection 