FPGA-Based Implementation of All-Digital QPSK Carrier Recovery Loop Combining Costas Loop and Maximum Likelihood Frequency Estimator

Figure 12

The joint simulation result of ModelSim and MATLAB under the condition of SNR = 20 dB for our QPSK ADCRL.

(a) ModelSim output of loop filter

(b) MATLAB processing of output of loop filter

(c) MATLAB processing of ModelSim the output of NCO and input of QPSK modulated signal