Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis

Algorithm 1

Autoidentify algorithm for identification of multiplication and allied operations.

Input: A wordlength optimized dataflow graph (DFG)

Output: Consolidated list of multiplication operations in three categories

(1)     Perform Breadth First Search (BFS) on DFG

(2)   At each level of DFG

(3)     If a constant value node is found

(4)     Perform a Depth First Search (DFS) with constant value node as root

         node to find its successor node

(5)     If the second input to successor node is labeled a variable, store the

         variable identity and the constant in a hash table: H(MUL)

(6)     EndIf

(7)     EndIf

(8)   End BFS

(9)   Identity (ID) = 0

(10) For each multiplication node

(11)   Check if successor node, SN is addition or subtraction else Step  9

(12)     Check if successor node SNN of SN is addition or subtraction

(13)        If (11) is TRUE

(14)        Check if second operand source of SNN is a MUL node

(15)        If (13) is TRUE

(16)        Collect all nodes in 9, 10, 11, and 13 as a partial graph

(17)        SN = SNN

(18)        Repeat 11 to 16 until (11) or (13) returns FALSE

(19)        Chain Detected = Yes

(20)       Length of chain = Number of ADD/SUB nodes

(21)        Chain ID = ID + 1

(22) EndFor

(23) Remove from H(MUL) all MUL nodes collected in Step  15.