Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis

Algorithm 2

Joint comparison and selection (JCS) algorithm.

Input: A collection of multiplication operations of three different types obtained from Algorithm A

Output: Ordered of multiplication operation instances identified for mapping to DSP blocks.

(1) Calculate the number of FAs required using Tables 4, 6, and 8 and (4)

(2) Calculate the number of AND gates required using (3)

  (Note that no AND gate is required when multiplying with constants)

(3) Calculate “Equivalent LUT Cost” for all SCM and variable-variable multiplication

  operations using (5)

(4) Calculate “Equivalent LUT Cost” for different sets of MCM operations using (5)

    (4.1) In each set, select the operation with the maximum “Equivalent LUT Cost”

   that is “MAX(Equivalent LUT Cost)”.

(5) Calculate “Equivalent LUT Cost” for different MULT-(ADD/SUBTRACT) Chains using (5)

    (5.1) In each set, select the multiplication operation with the maximum “Equivalent LUT Cost”

   that is “MAX(Equivalent LUT Cost)”.

(6) Remove multiplication operations part of MULT-(ADD/SUBTRACT) chains from the H(MULT) hash table

(7) Arrange multiplication operations from 5.1 and 6 in descending order of “Equivalent LUT Cost”

  as per Steps  (3), (4.1) and (5.1) to form list

(8) Map multiplication operations from the top in list to DSP blocks until DSP blocks are exhausted

(9) Map remaining multiplication operations to LUTs