Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis

Table 11

Result comparison between Vivado-HLS and proposed approach for 7-tap FIR filter.

Design	Vivado-HLS			Proposed approach
	CLK period required (ns)	CLK period achieved (ns)	DSP48	CLK period achieved (ns)	DSP48
7-tap FIR filter	3	5.819	9	2.413	7
	4	5.837	9
	5	6.083	9
	6	5.902	9