Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis

Table 2

Variation of actual (LUT), count (LUT), and DSP implementation.

		Actual; (LUT)	Count; (LUT); (2)	CLK (ns); (LUT Imp.)	DSP Imp.
16	8	128	254	6.307	1
24	8	184	392	6.883	2
32	8	240	510	7.734	2
32	32	1113	2750	12.511	4