| library IEEE; |
| use IEEE.STD_LOGIC_1164.all, IEEE.STD_logic_arith.all; |
| entity DFT3 is |
| port( |
| CLK: in STD_LOGIC; |
| START: in STD_LOGIC; |
| DRI: in std_logic_vector(15 downto 0); |
| DII: in std_logic_vector(15 downto 0); |
| DRO: out std_logic_vector(17 downto 0); |
| DIO: out std_logic_vector(17 downto 0)); |
| end DFT3; |
| architecture synt of DFT3 is |
| signal S1r,S2r,S3r,S5r,S6r,R1r,R2r: signed(17 downto 0); |
| signal S1i,S2i,S3i,S5i,S6i,R1i,R2i: signed(17 downto 0); |
| signal S4r,S4i: signed(17 downto 0); |
| signal CYC: natural range 0 to 3; |
| begin |
| CNTRL:process(CLK) begin |
| if rising_edge(CLK) then |
| if START =1 then |
| CYC<=0; |
| else |
| if CYC =2 then |
| CYC <=0; |
| else |
| CYC <=CYC +1; |
| end if; |
| end if; |
| end if; |
| end process; |
| CALC: process(CLK) begin |
| if rising_edge(CLK) then |
| case CYC is |
| when 0 => |
| S1r<= signed(SXT(DRI, S1rlength)); |
| S1i<= signed(SXT(DII, S1Ilength)); |
| S2r<=S1r − S2r; |
| S2i<=S1i − S2i; |
| R2r<= S1r; |
| R2i<= S1i; |
| S4r<= SHR(S3r, "010") − R1r; |
| S4i<= SHR(S3i, "010") − R1i; |
| S5r<=R1r − SHR(S4r, "011"); |
| S5i<=R1i − SHR(S4i, "011"); |
| S6r<= R2r − S5i; |
| S6i<= R2i + S5r; |
| when 1 => |
| S1r<= S1r + signed(DRI); |
| S1i<= S1i + signed(DII); |
| R2r<= S2r; |
| R2i<= S2i; |
| S3r<= S1r − signed(DRI); |
| S3i<= S1i − signed(DII); |
| S5r<=S5r + SHR(S4r, "1010"); |
| S5i<=S5i + SHR(S4i, "1010"); |
| S6r<=R2r; |
| S6i<=R2i; |
| when others=> |
| S1r<= S1r + signed(DRI); |
| S1i<= S1i + signed(DII); |
| S2r<= S1r + SHR(S1r, "001"); |
| S2i<= S1i + SHR(S1i, "001"); |
| S3r<= SHR(S3r, "010") − S3r; |
| S3i<= SHR(S3i, "010") − S3i; |
| S4r<= S3r + SHR(S3r, "0100"); |
| S4i<= S3i + SHR(S3i, "0100"); |
| R1r<=S3r; |
| R1i<=S3i; |
| S6r<= R2r + S5i; |
| S6i<= R2i − S5r; |
| end case; |
| end if; |
| end process; |
| DRO<= std_logic_vector(S6r); |
| DIO<= std_logic_vector(S6i); |
| end synt; |
