FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture

Sequences of GF<svg height="12.7178pt" id="M185" style="vertical-align:-3.42947pt" version="1.1" viewbox="-0.0498162 -9.28833 16.8673 12.7178" width="16.8673pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M300 -147C201 -63 143 98 143 270S200 602 300 686L282 710C136 610 70 450 70 271V270C70 89 136 -72 282 -170L300 -147Z" id="g113-41"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="346" vert-adv-y="346"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,4.498,0)"><path d="M570 304C570 398 525 448 414 448C385 448 343 445 312 434L329 511L321 518C297 504 262 482 244 460L233 411C195 397 159 381 128 358L135 332C160 347 189 360 224 373L111 -147C97 -210 84 -218 17 -231L13 -257L254 -247L259 -218L233 -216C183 -212 177 -202 189 -142L218 -1C238 -10 266 -12 283 -12C351 3 429 48 483 105C543 168 570 242 570 304ZM482 289C482 161 380 33 304 33C278 33 248 51 233 69L303 396C326 400 352 403 369 403C428 403 482 380 482 289Z" id="g113-113"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="593" vert-adv-y="593"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,12.208,0)"><path d="M275 270C275 450 212 609 64 710L45 686C145 604 203 442 203 270S147 -63 45 -147L64 -170C213 -68 275 89 275 270Z" id="g113-42"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="346" vert-adv-y="346"></glyph.data></g></svg> operations for EC point operations.

International Journal of Reconfigurable Computing

tab2

Table 2

Table 2: FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture 