FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture

Table 5

Performance comparison with exiting FPGA implementations.

Design	Field size	Platform	Area (slices)	Freq (MHz)	Time (ms)	TP (Kbps)
This work	160	Virtex-4	7,088	53	1.4	114
	192		8,590	48	2.3	83.5
	224		10,800	43	3.5	64
	256		13,158	40	5	51
This work	160	Virtex-II pro	6,492	40	1.9	84
	192		7,930	35	3.2	60
	224		9,308	31	4.9	45
	256		11,104	27	7.4	34
[21]	160	Virtex-4	12,415	60	2.2	72
	192		14,858	53	3.5	55
	224		17,331	47	5.4	41
	256		20,123	43	7.7	33
[18]	160	Virtex-II	3,433	40	7.1	22
	192		4,135	35	11.6	16.5
	224		4,808	33	16.8	13.3
[16]	192	Virtex-II pro	20,793	49	7.24	26
[32]	192	Virtex-II pro	3,173	93	9.90	19.3
[33]	256	Virtex-II pro	15,775	39	5.99	42.7
[20]	192	Virtex-II pro	8,972	43	4.47	42
	224		10,386	40	6.50	34
	256		11,953	36	9.38	27.2