Research Article
XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware
Table 2
The convolved output for input logic “
0” and
SR states with parity bits as output.
| | Encoder state | | |
| | 00000 | 0 | 0 | | 00001 | 1 | 1 | | 00010 | 0 | 1 | | 00011 | 1 | 0 | | 00100 | 0 | 0 | | 00101 | 1 | 1 | | 00110 | 0 | 1 | | 00111 | 1 | 0 | | 01000 | 1 | 1 | | 01001 | 0 | 0 | | 01010 | 1 | 0 | | 01011 | 0 | 1 | | 01100 | 1 | 1 | | 01101 | 0 | 0 | | 01110 | 1 | 0 | | 01111 | 0 | 1 |
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