FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Figure 7

Layer-level view of the pipeline timing diagram. (a) General case for a circulant- identity submatrix construction based QC-LDPC code (see Section 2) without pipelining. (b) Special case of the IEEE 802.11n QC-LDPC code used in this work without pipelining. (c) Pipelined processing of two layers for the general QC-LDPC code case in (a). (d) Pipelined processing of two layers for the IEEE 802.11n QC-LDPC code case in (b). This schedule is illustrated by the layer processing loop in the high-level decoder architecture shown in Figure 9. Here, represents the number of rows of .