FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Table 5

Block shift matrix showing the right-shift values for the valid blocks to be processed.

Layers	Blocks
		57	50	11	50	79	1	0	−1
	3	28	0	55	7	0	0	−1
	30	24	37	56	14	0	0	−1
	62	53	53	3	35	0	0	−1
	40	20	66	22	28	0	0	−1
	0	8	42	50	8	0	0	−1
	69	79	79	56	52	0	0	0
	65	38	57	72	27	0	0	−1
	64	14	52	30	32	0	0	−1
	45	70	0	77	9	0	0	−1
	2	56	57	35	12	0	0	−1
	24	61	60	27	51	16	1	0