FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

Table 8

Performance and resource utilization comparison, after mapping onto the FPGA, for versions with varying number of cores of the QC-LDPC decoder implemented on the NI USRP-2953R containing the Xilinx Kintex-7 (410t) FPGA.

Cores	1	2	4	5	6
Throughput (Mb/s)	420	830	1650	2060	2476
Clock rate (MHz)	200	200	200	200	200
Time to VHDL (min)	2.08	2.08	2.08	2.02	2.04
Total compile (min)	36	60	104	132	145
Total slice (%)	28	44	77	85	97
LUT (%)	18	28	51	62	73
FF (%)	10	16	28	33	39
DSP (%)	5	11	21	26	32
BRAM (%)	11	18	31	38	44