Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

<div>A CLB with 10 LUTs (<svg height="8.8423pt" id="M24" style="vertical-align:-0.2064009pt" version="1.1" viewbox="-0.0498162 -8.6359 38.4976 8.8423" width="38.4976pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M822 650H589L583 622C660 617 677 607 674 561C672 534 664 481 647 390L600 137H596L273 650H126L120 622C176 620 194 615 207 594C221 571 225 557 214 504L161 257C141 166 129 112 121 85C108 42 83 30 29 28L23 0H260L266 28C193 33 173 42 176 89C178 122 186 172 202 255L256 527H259L583 -8H612L690 390C708 481 720 535 728 558C744 603 756 619 816 622L822 650Z" id="g113-79"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="839" vert-adv-y="839" xpluscharwidth="10.907"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,14.542,0)"><path d="M535 323V373H52V323H535ZM535 138V188H52V138H535Z" id="g117-34"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="587" vert-adv-y="587" xpluscharwidth="22.173000000000002"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,25.805,0)"><path d="M384 0V27C293 34 287 42 287 114V635C232 613 172 594 109 583V559L157 557C201 555 205 550 205 499V114C205 42 199 34 109 27V0H384Z" id="g113-50"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="480" vert-adv-y="480" xpluscharwidth="32.045"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,32.045,0)"><path d="M241 635C89 635 35 457 35 312C35 153 89 -12 240 -12C390 -12 443 166 443 312C443 466 390 635 241 635ZM238 602C329 602 354 454 354 312C354 172 330 22 240 22C152 22 124 173 124 313S148 602 238 602Z" id="g113-49"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="480" vert-adv-y="480" xpluscharwidth="38.285000000000004"></glyph.data></g></svg>) and 3 shared pairs (<svg height="8.8423pt" id="M25" style="vertical-align:-0.2064009pt" version="1.1" viewbox="-0.0498162 -8.6359 29.3374 8.8423" width="29.3374pt" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"><g transform="matrix(.013,0,0,-0.013,0,0)"><path d="M600 480C600 590 528 650 384 650H143L137 622C222 614 225 607 210 531L130 127C113 41 106 36 23 28L17 0H294L300 28C204 36 195 42 212 127L243 284L314 263C327 263 339 263 352 264C465 271 600 337 600 480ZM508 481C508 351 402 304 329 304C289 304 265 311 250 317L295 559C302 594 310 606 323 611C335 616 350 619 367 619C455 619 508 573 508 481Z" id="g113-81"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="617" vert-adv-y="617" xpluscharwidth="8.021"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,11.658,0)"><path d="M535 323V373H52V323H535ZM535 138V188H52V138H535Z" id="g117-34"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="587" vert-adv-y="587" xpluscharwidth="19.289"></glyph.data></g><g transform="matrix(.013,0,0,-0.013,22.921,0)"><path d="M285 378C315 398 338 416 353 432C373 451 384 474 384 503C384 579 325 635 236 635H235C182 635 136 610 108 579L65 516L85 496C110 533 150 575 205 575C258 575 300 543 300 481C300 407 232 369 141 339L147 310C163 315 188 321 211 321C268 321 338 284 338 192C338 94 288 40 217 40C160 40 119 68 93 91C85 98 77 97 69 91C60 84 47 71 46 58C44 46 48 35 62 22C75 10 116 -12 162 -12C234 -12 424 62 424 224C424 297 373 359 285 376V378Z" id="g113-52"></path><glyph.data ascent="3473" descent="-2876" horiz-adv-x="480" vert-adv-y="480" xpluscharwidth="29.161"></glyph.data></g></svg>).</div>

International Journal of Reconfigurable Computing

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Figure 2

Figure 2: Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing 