FPGA Implementation of Reconfigurable Finite State Machine with Input Multiplexing Architecture Using Hungarian Method

Table 4

Iterative implementation of the Reconfigurable FSMIM-S architecture on Virtex-6.

Iteration	FSM included in the; particular iteration	#LUTs occupied in the; particular iteration	Maximum operating; frequency	Maximum path; delay	#LUTs occupied by the FSM; (#LUTs in the current iteration − #LUTs in the previous iteration)
0th	s1494	42	810.17 MHz	4.571 ns	42
1st	sand	79	779.271 MHz	4.778 ns	37
2nd	styr	105	775.164 MHz	4.455 ns	26
3rd	planet	137	728.704 MHz	4.609 ns	32
4th	s832	199	725.005 MHz	5.381 ns	62
5th	cse	230	722.335 MHz	5.140 ns	31
6th	s386	249	720.643 MHz	5.662 ns	19
7th	ex6	255	715.231 MHz	4.967 ns	6
8th	mc	269	706.889 MHz	4.526 ns	14
9th	planet1	303	676.338 MHz	5.098 ns	34
10th	s1488	330	671.760 MHz	4.486 ns	27
11th	s208	349	665.181 MHz	3.014 ns	19

Note. #LUTs denotes the number of LUTs in ISE.