ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures

Table 1

Synthesis results for each optimization step.

	Optimization	Slice	FF	LUT	BRAM (18K)	Time (ms)
SW version running at 380 ms on core i7@ 2.7 GHz and 16 GB of RAM
#1	First synthesizable design	X	2637	5918	7392	X
#2	Hor. then ver. aggregation	898	1743	2735	155	30080
#3	Ver. then hor. aggregation	859	1758	2659	113	22410
#4	In both directions	1400	2552	3738	75	8163
#5	Arbit. prec. data types	983	1525	2567	47	5786
#6	I/O interface protocols	996	1575	2619	49	6307
#7	Grouping pixels	1135	1820	3080	49	5865
#8	Task-level parallelism	1110	2002	3339	67	2658
#9	Calculating 4 disp. lines	2790	4578	7796	102	815
#10	Calculating 8 disp. lines	5012	8502	14027	204	432
#11	Calculating 12 disp. lines	6594	12563	18476	252	339
#12	Loop pipelining	1161	2004	3546	67	1174
#13	False dependency	1115	2030	3433	67	1002
#14	Data-level parallelism	2771	6365	8155	59	313