Research Article
Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation
Table 8
Vivado critical synthesis warnings.
| | Project | Variant | BRAM instantiation | Multi-driven nets | Tri-cell conversion |
| | LeWiz LMAC1 | LMAC_CORE1_AXIS | — | 12 | — | | LeWiz LMAC1 | LMAC_CORE1_AXIS_XPM_FIFO | — | 12 | — | | LeWiz LMAC1 | LMAC_CORE_TOP | — | 12 | — | | LeWiz LMAC1 | LMAC_CORE_TOP_XPM_FIFO | — | 12 | — | | Litex Liteeth | liteeth | — | — | 1 | | Litex Liteeth | liteeth-rgmii | — | — | 1 | | Opencores Ethernet Tri Mode | clk_reg_is_clk_user | 12 | — | — | | Opencores Ethernet Tri Mode | clk_reg_is_not_clk_user | 12 | — | — | | Opencores Ethmac | — | — | — | 32 | | Opencores Minimac | — | — | — | 1 | | P. Kerling Ethernet MAC | pkerling_ethernet_mac | — | — | 1 | | P. Kerling Ethernet MAC | pkerling_ethernet_mac_with_fifos | — | — | 1 | | WGE 100 | — | — | — | 1 |
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